We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23973

8.2i Virtex-5 MAP - Write address line of RAM128X1D incorrectly optimized when SPO is unused


I have instantiated a RAM128X1D distributed RAM primitive and targeted it to a Virtex-5 device. The SPO output is marked as being OPEN in the VHDL, meaning that I do not want to use the output. I want to write into the top of the RAM and read out of the bottom of the RAM. The optimization that occurs due to the unused SPO incorrectly removes the 7th address line so that you can read from all 128 locations, but only write to 64 locations.


This problem has been fixed in the latest 8.2i Service Pack available at: 

The first service pack containing the fix is 8.2i Service Pack 3.

AR# 23973
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article