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8.2i ISE - PLL_ADV VHDL model does not phase shift when CLKFBOUT_MULT and CLKOUTx_DIVIDE attributes are set to 1

AR# 23975

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Topic XST General
Last Updated 09/12/2006
Status Active
Description

Keywords: Virtex-5, SP2, UniSim, library, VHDL

The VHDL model of the PLL_ADV primitive does not phase shift when CLKFBOUT_MULT and CLKOUTx_DIVIDE attributes are set to 1.

Solution

This problem has been fixed in the latest 8.2i Service Pack 3 available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp


 
 
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