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AR# 23975

8.2i ISE - PLL_ADV VHDL model does not phase shift when CLKFBOUT_MULT and CLKOUTx_DIVIDE attributes are set to 1

Description

The VHDL model of the PLL_ADV primitive does not phase shift when CLKFBOUT_MULT and CLKOUTx_DIVIDE attributes are set to 1.

Solution

This problem has been fixed in the latest 8.2i Service Pack 3 available at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

AR# 23975
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article