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8.2i UniSim, Simulation - PLL output ( CLKOUT0) is 180 degrees out of phase with clock input ( CLKIN1)

AR# 23983

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Topic Unisim
Last Updated 09/12/2006
Status Active
Description

Keywords: UniSim, simulation, ModelSim, NC-Verilog, PLL, Phase shift, VCS

PLL output ( CLKOUT0) is 180 degrees out of phase with clock input ( CLKIN1) when CLKFBOUT_MULT = 8 and CLKOUT0_DIVIDE = 8. Why?

Solution

This problem has been fixed in the latest 8.2i Service Pack 3 available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

 
 
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