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Virtex-7 FPGA VC709 Connectivity Kit
All the necessary hardware, software and IP to quickly power through the evaluation and development of connectivity systems.
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Jumpstart your design development with the Kintex-7 FPGA KC705 Evaluation Kit - all the basic components of hardware, design tools, IP, and pre-verified reference designs including a targeted design enabling high-performance serial connectivity and advanced memory interfacing.
Xilinx is the world’s leading provider of All Programmable technologies and devices, beyond hardware to software, digital to analog, and single to multiple die in 3D ICs.
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PLL output ( CLKOUT0) is 180 degrees out of phase with clock input ( CLKIN1) when CLKFBOUT_MULT = 8 and CLKOUT0_DIVIDE = 8. Why?
This problem has been fixed in the latest 8.2i Service Pack 3 available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp