In cases where the buffer throttles the logical layer on the third or fourth beat of a 40 deep word or larger packet when no previous packet is in the pipe, the logical layer might replicate one of the packet beats. This leads to an extra beat in the middle of the packet and oversized packets when the packet being sent is max size.
This issue will be fixed in Serial RapidIO v4.1 release expected to be available in February 2007.
If you need a fix for this issue sooner, please contact Xilinx Technical Support at:
Please provide three XCO files from v3.1 core.