The example design for Aurora 2.4 does not work properly at speeds below 1.25 Gb/s. The failure occurs in both simulation and in hardware.
To work around this problem, make the following modifications to the MGT and Cal Block attributes:
MGT Attribute: change the ENABLE_DCDR from FALSE to TRUE.
Cal Block Attributes*:
- C_RXOUTDIV2SEL_A: set to the RXOUTDIV2SEL value from MGT A.
- C_RXOUTDIV2SEL_B: set to the RXOUTDIV2SEL value from MGT B.
* NOTE: The Aurora 2.4 example design assumes CES2/3 silicon is used and automatically instantiates Cal Block 1.2.1. The Cal Block changes listed in this Answer Record are necessary only for CES2/3 silicon and Cal Block 1.2.1. If Cal Block 1.4.x is used in conjunction with CES4 silicon, the Cal Block attribute changes are not necessary.