AR #23995 - LogiCORE SPI-4.2 (POS-PHY L4) - What is the power consumption of SPI-4.2 Core in Virtex-5 device?

AR#	23995
Part	IP-Telecom-SPI-4.2
Last Modified	2008-01-24 00:00:00.0
Status	Active
Keywords	system, packet, interface, SPI-4.2, PL4, POS, PHY, Level 4, update, CORE Generator, CORE Generator, v8.1 networking, packet, over, sonet, sonnet, full, rate, oc-192, dpa, dynamic, alignment, static, spi, spi-4.2, spi4.2, spi4-2, power, consumption, virtex-5

Solution

The following results were obtained using Xilinx Power Estimator Spreadsheet v8.2 available at:
http://www.xilinx.com/products/design_resources/power_central/

Three design cases were used to estimate the power consumption. All three designs use design example delivered with Xilinx SPI-4.2 v8.1 Core. Each design consists of Sink core, Source core and the loopback module. The target device is 5vlx30 ff324, commercial speed grade, and LVDS IO type is used for the status pins.

Design 1:
Static Alignment, @700 Mbps
Tsclk - DCM
SysClk - global
RDClk - global

Design 2:
DPA Standard, @1Gbps
TSClk - DCM
SysClk - global
RDClk - global

Design 3:
DPA Continuous, @1.25Gbps
TSClk - DCM
SysClk - global
RDClk - global


------------------------------------Design 1 (Static 700) ----------Design 2 (DPA) ---------- Design 3 (DPA Cont 1.25G)
Static power (W) ....................0.491.............................................0.510............................................0.509
Dynamic power (W).................0.935............................................1.149............................................1.337
Total (W).................................1.415............................................1.659............................................1.846

These numbers are estimated power of the entire design consisting of Sink, Source and the loopback design.