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AR# 23995

LogiCORE SPI-4.2 (POS-PHY L4) - What is the power consumption of an SPI-4.2 Core in a Virtex-5 device?

Description

What is the power consumption of an SPI-4.2 Core in a Virtex-5 device?

Solution

The following results were obtained using Xilinx Power Analyzer tool (v10.1.03) along with the example design simulation.

Three design cases were used to estimate the power consumption. All three designs use the example design delivered with the Xilinx SPI-4.2 v8.6 Core. Each design consists of Sink core, Source core and the loopback module. The target device is xc5vlx50-ff676-1, commercial speed grade, and LVTTL I/O type is used for the status pins.

Design 1:  
Static Alignment, @ 700 Mb/s
64-bit User Interface
TSClk - DCM 
SysClk - global  
RDClk - global 

Design 2: 
DPA @ 700 Mb/s
64-bit User Interface
TSClk - DCM 
SysClk - global 
RDClk - global 

Design 3: 
DPA @ 1.2 Gb/s
128-bit User Interface
TSClk - DCM 
SysClk - global 
RDClk - global 

   Design 1 (Static 700)  Design 2 (DPA 700)  Design 3 (DPA 1.2G)
 Quiescent power (W)  0.661  0.660  0.700
 Dynamic power (W)  1.581  1.556  1.839
 Total (W)  2.242  2.216  2.539

These numbers represent the estimated power of the entire design consisting of Sink, Source, and the loopback design. 

Revision History 
01/24/2008 - Initial Release 
01/21/2009 - Updated for v8.6 core
03/02/2010 - Updated with XPA numbers

 


AR# 23995
Date Created 01/24/2008
Last Updated 05/20/2014
Status Archive
Type General Article