LogiCORE FIFO Generator v3.2 - NCSIM warning seen when targeting Virtex-5
Description
Keywords: CORE, CORE Generator, COREGen, IP, update, 8.2i, ip2_im, FIFO, generator, fifogen, asynchronous, synchronous, common, clocks, memory, block RAM, BRAM, RAMB16, FIFO16, asynch, asymmetric, non-symmetric, first, word, fall, through, fwft, virtex-5, v5, ncsim, nclab
FIFO Generator v3.2 Core, when implemented with Virtex-5 common clock or independent clock block RAM (uses the Block Memory Generator v2.2 Core) , results in several NCLAB warnings while running timing simulation.
ncelab: *W,BNDMEM (/proj/ipco/clibs/IPpub/ius/5.5/lin/lib/simprims_ver/simprims_ver_virtex5_source.v,3444|77
): memory index out of declared bounds [4.2.2(IEEE)].