We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24015

8.2i EDK SP2, Spartan-3E Starter Kit - BSB created design fails DDR Memory Test


DDR Memory Test Fails on the Spartan-3E Starter Kit in EDK 8.2i.


Solution 1:

Change the mode pins to JTAG/BSCAN by removing the jumpers from M0 and M2 and keeping the jumper on M1.

Solution 2:

If you have the OPB Ethernet in the design, please refer to SR 23812. BUFGs are unnecessarily inserted in the RX and TX clock paths.

AR# 24015
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article