UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24018

LogiCORE FIFO Generator v3.2 - Timing simulation fails with illegal connection to module port "TIEOFFREGCEAL"

Description

Keywords: CORE, CORE Generator, IP, update, 8.2i, FIFO, generator, fifogen, asynchronous, synchronous, common, clocks, memory, block RAM, BRAM, RAMB16, FIFO16, asynch, asymmetric, non-symmetric, first, word, fall, through, fwft, Virtex-5, Virtex, V5, fifo18_36, error

When running timing simulation for a Virtex-5 design containing a FIFO Generator created with Build-In-FIFO, the following simulation error occurs:

"Error message in ncsim for Verilog simulation:
ncelab: *E,CUVPOM (routed.v,757|17): Illegal connection to module port 'TIEOFFREGCEAL'

Error message in ncsim for VHDL simulation:
routed.vhd: TIEOFFREGCEAL => GLOBAL_LOGIC1,
ncvhdl_p: *E,FMLUNK (routed.vhd,754|18): unknown formal designator 87[4.3.3.2] 93[4.3.2.2]."

Solution

This error occurs when the FIFO is created with the FIFO18_36 primitive. The generated simulation netlist incorrectly contains a reference to the TIEOFFREGCEAL pin.

This issue is fixed in the Virtex-5 Simulation Patch Bundle.

Contact Xilinx Technical Support to receive this patch:
http://www.xilinx.com/support/mysupport.htm

This issue is fixed in the ISE 9.1i design tools.
AR# 24018
Date Created 09/04/2007
Last Updated 02/15/2007
Status Active
Type General Article