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AR# 24024

iMPACT - How can the data from the Status Register be used to debug configuration issues?


Reading the on-chip Status Register is an important part of troubleshooting configuration issues.

The information extracted from the Status Register will help determine the stage of configuration and where a failure has occurred.

As such, it is important for you to be able to understand the key stages of configuration and correlate that to the bits read from the Status Register.

It is best to test input files via iMPACT and then move on to board-level configuration.

If configuration attempts are failing, use iMPACT to gain access to the Status Register of the device after a configuration attempt has failed.

For more iMPACT Error Articles and other Configuration Related Articles, see (Xilinx Answer 34104).


The Status Register can be read via iMPACT from any Virtex or Spartan family devices.

The Status Register contains the current status of the configuration process and is independent of the configuration methods.

Bits in the status register will be initialized when PROG or the power is pulsed.

As configuration occurs, different bits in the Status Register become set denoting the stage of the configuration process the device is in.

To use the Status Register for debugging, run a configuration attempt on the device.

After this has completed, use iMPACT to initialize the chain and select Debug -> Read Status Register on the targeted device.

This operation in iMPACT will not affect the Status Register contents of the device, and will report this in the console window and "_impact.log" file.

Text similar to the following should appear in the iMPACT console window:

Command: ReadStatusRegister -p 0
// *** BATCH CMD : ReadStatusRegister -p 1
Chain TCK freq = 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Reading status register contents...
CRC error : 0
DCM locked : 1
DCI matched : 1
status of GTS_CFG_B : 0
status of GWE : 0
status of GHIGH : 0
value of MODE pin M0 : 0
value of MODE pin M1 : 0
value of MODE pin M2 : 0
value of CFG_RDY (INIT_B) : 1
DONEIN input from DONE pin : 0

* NOTE: This is a sample derived from the Status Register of an un-configured Spartan-3E device.

Below is information regarding each bit in the Status Register.

Further information for these settings is listed in the Configuration User Guides or Data Sheets.

CRC error - The CRC error bit indicates whether the bit stream has passed "0" or failed "1" the CRC checking.
INIT_B will also go Low when CRC errors occur, unless JTAG configuration is being used.
CRC errors are typically due to clocking or SI issues on the board.
If a CRC error occurs, try slowing down the configuration speed, or investigating the SI characteristics of the configuration signals (in particular, the clock line).

DCM locked - The DCM locked bit is a flag for when the DCM has been locked prior to DONE going High.
This property is set by the BitGen setting "Release DLL (Output Events)", and the ".bgn" file LCK_cycle will be "1".
If this option has been set and DCM locked = "0", the DCMs are not locked and the Start-Up sequence hangs.
First, remove this option and try the files again to ensure that this is the problem.
Next, analyze why the DCMs do not lock.

DCI matched - The DCI matched bit is a flag for when the DCI has been matched prior to DONE going High.
This property is set by the BitGen setting "Match Cycle" and the ".bgn" file "MATCH_cycle" will be "1".
If this option has been set and DCI matched = "0", the DCI does not match and the Start-Up sequence hangs.
First, remove this option and try the files again to ensure that this is the problem.
If this resolves the issue, the DCI matching issues will also need to be addressed.

GTS_CFG_B - The GTS_CFG_B bit = 1 indicates that all device I/Os have been released from 3-state mode.
If this bit is a "0", then the event has not happened and all I/O pins are still in a 3-state condition.
This bit is part of the Start-Up sequence specified by BitGen and can be found in the ".bgn" file.
If this bit is a "0", this stage of the Start-Up sequence never finished, and GHIGH and the CRC bits should be checked.

GWE - The GWE status bit = 1 indicates that flip-flops have been write enabled.
This bit is released in the Start-Up sequence that is listed in the ".bgn" report.
If this bit is a "0", this stage of the Start-Up sequence never finished, and GHIGH and the CRC bits should be checked.

GHIGH - The GHIGH bit indicates if the data load completed and the device is ready to enter the Start-Up sequence.
A logical value of "0" indicates that the data load to the device did not complete, and a "1" indicates that the data portion of the bit file completed successfully.
If this has been set, all of the configuration data has been loaded into the device.

MODE pin(s) - The MODE pin values are sampled when INIT_B goes High, and they determine the configuration mode of the device.
The configuration mode will not affect the functionality of the JTAG pins, which are always available regardless of the mode set.
Always double-check the MODE pin settings if configuration fails.

CFG_RDY (INIT_B) - The CFG_RDY bit reflects the status of the INIT_B pin.
Configuration can occur only if INIT_B is a logical "1".
If this pin is "0",check the Start-Up sequence bits to see if the Start- Up sequence has completed, as this pin becomes a User I/O in some devices.
If the Start-Up sequence has not completed, check the CRC bit for CRC errors.
If this is not the case, pulse PROG and see if INIT_B goes High.
If this does not occur, check the power supplies for the device.

DONEIN input from DONE pin - The DONEIN bit reflects the status of the DONE pin.
When configuration is complete and the device has passed the Start-Up sequence successfully, the DONE pin should be a logical "1".
If this bit has been set and the device is not operational, check the GTS and GWE, as the device might not be getting through the Start-Up sequence listed in the ".bgn" file.
If it has not been set, this stage of the Start-Up sequence has not been successfully completed.
This can occur if the DONE pin pullUp is not strong enough, and the DONE pin does not rise within one clock cycle, or if there were CRC errors or other problems during the data load, and the CRC and GHIGH bits should be checked.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34104 Configuration Design Assistant N/A N/A
51233 Virtex-7 FPGA VC707 Evaluation Kit - Board Debug Checklist N/A N/A
AR# 24024
Date Created 09/04/2007
Last Updated 02/09/2015
Status Active
Type General Article
  • FPGA Device Families