We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24026

LogiCORE SPI-4.2 (POS-PHY L4) v10.5 and earlier - Locked_RDClk (from RDClk DCM) might be de-asserted after PhaseAlignRequest


During operation (simulation or hardware) of the SPI-4.2 Sink Core with Global Clocking and DPA Clock Adjustment option, the "Locked_RDClk" signal (from the RDClk DCM) might be de-asserted and/or the "DcmLost_RDClk" signal might assert after PhaseAlignRequest is asserted.


This Answer Record applies only to Virtex-4 and Virtex-5 FPGA. Virtex-6 FPGA does not support the "Insert IDELAY on RDClk" feature for Global Clocking. 

This is an issue only when the Sink Core uses Global Clocking and the DPA Clock Adjustment option along with the "Insert IDELAY on RDClk" option. When PhaseAlignRequest is asserted, the IDELAY goes through the reset process and the clock stops toggling momentarily. This causes the DCM to lose lock. In addition, the DPA logic shifts the clock using the IDELAY primitive, and this action might cause the Locked_RDClk lock signal from the DCM to de-assert, or the DcmLost_RDClk signal to assert. To avoid issues with core operation, momentary de-assertions of Locked_RDClk and momentary assertions DcmLost_RDClk signals should be ignored after PhaseAlignRequest has been asserted. 

Revision History 

09/21/2006 - Initial Release 
06/24/2009 - Updated with Virtex-6 FPGA information
10/27/2011 - Update issue description

AR# 24026
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • More
  • Virtex-4 SX
  • Virtex-4Q
  • Virtex-4QV
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Less
  • SPI-4 Phase 2 Interface Solutions