We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24027

8.2i IP Update 2 - When compiling XilinxCoreLib, an error occurs: "Error-[URMI] Instances with unresolved modules remain in the design"


Keywords: networking, Ethernet, MAC, XAUI, gigabit, SPI, SPI4, SPI42, SPI-4.2, SPI4.2, PL4, GFP, Tri-Mode, generic, framing, procedure, SONET, system, packet, interface, fibre, channel, DVB-ASI, FIFO, fifo16, cam, asynchronous, 8b10b, decoder, embedded, Aurora, wrapper, PCI, PCI-X, PCI32, PCI64, PCI-X, PIPE, PCI Express, UCF Generator, counter, DSP, Binary Counter, Comparator, Complex Multiplier, Distributed Arithmetic FIR Filter, DVB S2 FEC Encoder, Floating-point Cores, MAC, MACC, Pipelined Divider, RAM-based Shift Register, TCC Encoder 3GPP, LogiCORE, CORE Generator , VLYNQ , CAN , vcs, vcs_x, Verilog, CompXLib

When compiling XilinxCoreLib library, I receive the following error:

"Error-[URMI] Instances with unresolved modules remain in the design.
Invalid instantiation at: "
CoreLib_ver_source.v ", 27631: LUT1 N_6358_i("


To successfully compile the library, remove the following from the "verilog_analyze_order" file:


The file "verilog_analyze_order" is located in your ISE 8.2i installation directory (e.g., C:\Xilinx\verilog\src\XilinxCoreLib\).

AR# 24027
Date 10/13/2009
Status Archive
Type General Article
Page Bookmarked