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AR# 24041

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v8.0 - Release Notes and Known Issues for 8.2i IP Update 2 LXT Supplement (8.2i_IP2_LXTsup)


This Answer Record contains the Release Notes for the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v8.0 Core, which was released in 8.2i IP Update 2 LXT Supplement and includes the following:  


- New Features in v8.0 

- Bug Fixes in v8.0 

- Known Issues in v8.0 


For installation instructions and design tools requirements, see (Xilinx Answer 24008).


New Features in v8.0 


- Support added for Virtex-5 LXT 

- Updated Virtex-4 RocketIO configuration to change the CDR mode (this core previously used the digital oversampling receiver). This has now been switched to Analog CDR to reduce power consumption. 

- Improved example design hierarchy for core portability. 

- Improved example design to fully support Virtex-4 and Virtex-5 RocketIO pairs. 

- Improved CORE Generator GUI. 


Bug Fixes in v8.0 


- None. 


Known Issues in v8.0 


- Virtex-5 LXT ES silicon requires transmit signals between the fabric and GTP to be registered and locked down in order to meet timing. The example design ucf provides LOC constraints for a 5VLX50T GTP_DUAL_X0Y2. If a different device or GTP will be used, refer to (Xilinx Answer 24165) for information on how to generate the correct constraints. 


- For Virtex-5 LXT Verilog SGMII designs, a typo must be corrected in the "<component_name>_block.v" example design wrapper file. For information on how to correct this, refer to (Xilinx Answer 24327)


- For Virtex-4 1000BASE-X or SGMII implementations recommended GT11 attribute values for RXVCODAC_INIT and VCODAC_INIT for v4.3 with ACDR have changed. RXVCODAC_INIT and VCODAC_INIT should be changed from "0000000000" to "0000000101". This has been fixed in v4.4 of the core availible in 9.1i IP Update1, March 2007.

AR# 24041
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article