UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24042

Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper v1.1 - Release Notes and Known Issues for 8.2i IP Update 2 LXT Supplement (8.2i_IP2_LXTsup)

Description

This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.1, which was released in the 8.2i IP Update 2 LXT Supplement, and includes the following: 

 

- General Information  

- Known Issues  

 

For installation instructions and design tools requirements, see (Xilinx Answer 24307).

Solution

Initial Release of Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper 

 

- Supports automatic generation of HDL wrapper files for the Virtex-5 LXT Tri-Mode Ethernet MAC 

- Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII and 1000Base-X PCS/PMA configurations are supported) 

- Provides a FIFO-based example design 

- Provides a demonstration testbench for the selected configuration 

 

Known Issues 

 

- For designs using 1000BASE-X or SGMII, the Virtex-5 LXT ES silicon requires transmit signals between the fabric and GTP to be registered and locked down in order to meet timing. The example design UCF provides LOC constraints for a 5VLX50T GTP_DUAL_X0Y2. If a different device or GTP will be used, please refer to (Xilinx Answer 24166) for instructions on how to generate the correct constraints. 

 

- In the 8.2i tools, it is possible to receive incorrect timing failures for RGMII timing simulation. For more information on this, refer to (Xilinx Answer 24284). This issue will be fixed in 9.1i.

AR# 24042
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article