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AR# 24043

LogiCORE XAUI v7.0 - Release Notes and Known Issues for 8.2i IP Update 2 LXT Supplement (8.2i_IP2_LXTsup)


This Answer Record contains the Release Notes for the LogiCORE XAUI v7.0 Core which was released in 8.2i IP Update 2 LXT Supplement and includes the following:

- New Features in v7.0

- Bug Fixes in v7.0

- Known Issues in v7.0

For installation instructions and design tools requirements, see (Xilinx Answer 24008).


New Features in v7.0

- Support added for Virtex-5 LXT

- Improved example design hierarchy for core portability

- Virtex-4 GT11s now configured for low transmit latency

- Virtex-4 Channel Bonding Monitor added to restart channel bonding if there is a channel bonding failure

Bug Fixes in v7.0

- CR 415644 - User guide does not provide details on soft reset

- CR 415432 - Tab key does not traverse IP GUI fields in the proper order

- CR 415588 - ALIGN_COMMA_WORD GT11 attribute is incorrect

Known Issues in v7.0

1. Virtex-5 LXT ES silicon requires transmit signals between the fabric and GTP to be registered and locked down in order to meet timing. The example design "rocketio_wrapper.v/vhd" provides LOC constraints for a 5VLX50T GTP_DUAL_X0Y0 and GTP_DUAL_X0Y1. If a different device or GTP location will be used, please refer to (Xilinx Answer 24168) for instructions on how to generate the correct constraints.

2. Virtex-5 XAUI timing simulation fails. GTP_DUAL pins remain at 'X'. A fix for this issue is currently be investigated.

3. For Virtex-5 GTPs in order to successfully use the Transmit Buffer Bypass and TX Phase Alignment features in the Virtex-5 GTPs, the following attributes settings will need to be added to the ucf:

INST *xaui_block/rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i

PMA_COM_CFG = "90'h00000000000000000000450";

INST *xaui_block/rocketio_wrapper_i/tile1_rocketio_wrapper_i/gtp_dual_i

PMA_COM_CFG = "90'h00000000000000000000450";

4. For XAUI v7.0 the Virtex-4 GT11 settings were changed to use Low Latency, TX Buffer Bypass mode with Channel Deskew, but this has been found to generate a fair bit of skew at the pins. The below patch changes the GT11 back to Low Latency Buffered Mode with Channel Deskew.

5. For Virtex-4 designs there is a bug in the VHDL wrapper file "chanbond_monitor.vhd". Currently, the channel bonding time-out counter does not start. On line 292 'enable_cnt_r' should be changed to 'enable_cnt2_r'. Below is corrected code:

-- CB_SEARCH Timeout Counter

process (CLK, enable_cnt2_r)


if enable_cnt2_r = '0' then

--if enable_cnt_r = '0' then --previous code

cnt2_r <= (others => '0');

elsif CLK'event and CLK = '1' then

cnt2_r <= cnt2_r + 1;

end if;

end process;

6. For Virtex-5 Verilog example design in the "<core_name>_block.v" file, the change below should be made to the reset. Current Code:

"// reset the rx side when the buffer overflows / underflows

always @(posedge clk156)


if ( |mgt_rxbuferr )

mgt_rx_reset <= 1'b1;


mgt_rx_reset <= 1'b0;


1'b1 should be 4'b1111 and 1'b0 should be 4'b0000

7. Virtex-4 Verilog example design has GT11 comma alignment inputs driven by incorrect signals. This could cause rx comma alignment/synchronization to not function correctly in hardware. Refer to (Xilinx Answer 29058) for more information.


If using Virtex-4 to resolve issues 4, and 5 from the list of issues above, apply the following patch to the Xilinx ISE installation with the 8.2i Service Pack 3 and IP Update 2 LXT Supplement.


1. Install the patch by extracting the contents of the ".zip" or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.


Determine the Xilinx installation directory by entering the following at the command prompt:

echo %XILINX%

UNIX or Linux

Determine the Xilinx installation directory by entering the following:

echo $XILINX

NOTE: You might be required to have system administrator privileges to install the patch.

2. After installing the patch, regenerate the XAUI Core from CORE Generator. The core and supporting files produced will contain the updates mentioned above.

AR# 24043
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article