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AR# 24046

LogiCORE Endpoint Block for PCI Express v1.2 - Release Notes and Known Issues for 8.2i IP Update 3 (8.2i_IP3)

Description

This Answer Record contains Release Notes and installation information for LogiCORE Endpoint Block for PCI Express v1.2.

Solution

A CORE Generator update (8.2i IP Update 3) is available for the LogiCORE Endpoint Block for PCI Express v1.2. This must be downloaded and installed on top of your current 8.2i sp3 IP Update 3 installation. For general information about this update, see (Xilinx Answer 24266). This update can be found at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp.

LogiCORE Endpoint Block for PCI Express v1.2

General Information

The Virtex-5 LXT device contains a dedicated PCI Express Endpoint Block. Xilinx recommends the use of one of the two available wrappers produced by CORE Generator when targeting the PCI Express Endpoint Block in Virtex-5 LXT. Two wrappers are available, each with its own unique features. For more information on the wrappers, refer to:

http://www.xilinx.com/ipcenter/V5LXT_pcie_ep_sel_guide/index.htm

Known Issues

--A User Guide for the LogiCORE Endpoint Block for PCI Express v1.2 will be released by the end of January 2007. Until then, you can refer to the Virtex-5 LXT User Guide for the PCI Express block located at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
Navigate to FPGA Device Families -> Virtex-5 -> "Virtex-5 PCI Express Endpoint Block User Guide" (UG197).

--When using a -1 speedgrade, timing failures might occur when implementing a x4 or x8 core design using 250 MHz for the transaction interface frequency or on the 250 MHz interface between the PCI Express block and the GTP transceivers. Note that the transaction interface clock domain is different from the system reference clock input. Regardless of the system reference clock input frequency (either 100 MHz or 250 MHz), the transaction interface frequency can be either 125 MHz or 250 MHz. For more information on selecting the transaction interface clock frequency, please refer to the Virtex-5 LXT PCI Express Endpoint Block User Guide located at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
Navigate to FPGA Device Families -> Virtex-5 -> "Virtex-5 PCI Express Endpoint Block User Guide" (UG197).

This issue will be fixed with the ISE 9.1i IP Update 1 core release planned for February 2007.

--The input pin L0MSIREQUEST0[3:0] is not supported and is tied to 0000b in the wrapper. To generate an MSI packet, the user application should form the packet as it would any outgoing memory write transaction. The information for the MSI packet can be gathered by reading the MSI capability structure from the configuration management port.

--See the "readme.txt" file produced along with the generated core files for other known issues at the time of the release.

Previous Release Information

PCI Express Endpoint Block v1.1

Known Issues

--A User Guide for the PCI Express Endpoint Block v1.1 will be released by the end of January 2007. Until then, you can refer to the Virtex-5 LXT PCI Express Endpoint Block User Guide located at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
Navigate to FPGA Device Families -> Virtex-5 -> "Virtex-5 PCI Express Endpoint Block User Guide" (UG197).

--When using a -1 speedgrade, timing failures might occur when implementing a x4 or x8 core design using 250 MHz for the transaction interface frequency or on the 250 MHz interface between the PCI Express block and the GTP transceivers. Note that the transaction interface clock domain is different from the system reference clock input. Regardless of the system reference clock input frequency (either 100 MHz or 250 MHz), the transaction interface frequency can be either 125 MHz or 250 MHz. For more information on selecting the transaction interface clock frequency, please refer to the Virtex-5 LXT PCI Express Endpoint Block User Guide located at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
Navigate to FPGA Device Families -> Virtex-5 -> "Virtex-5 PCI Express Endpoint Block User Guide" (UG197).

This issue will be fixed with the ISE 9.1i IP Update 1 core release planned for February 2007.

--See the "readme.txt" file produced along with the generated core files for other known issues at the time of the release.

AR# 24046
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article