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AR# 24048

LogiCORE Block Memory Generator - When running simulation or HDL Synthesis tools, an error occurs stating that WE, WEA, or WEB has an incorrect type of std_logic_vector(0 downto 0)


Keywords: CORE, COREGen, CORE Generator, IP, update, 8.2i, ip2_im, mem, memory, synch, asymmetric, nonsymmetric, non-symmetric, block RAM, RAMB, BRAM, RAMB16, RAMB, simulation, UniSim, SimPrim, unisims, simprims, NetGen, sdf, v2.2, coe, simulator, mti, ModelSim, std_logic, std_logic_vector

When running simulation or HDL synthesis tools with Block Memory Generator Core, an error might occur stating that the signal WE, WEA, or WEB has an incorrect type of std_logic_vector(0 downto 0).

This is commonly experienced by customers who migrate from the old block memory core to the new Block Memory Generator. They now need to connect the write enable signal of the design that is 1-bit wide "std_logic" to a write enable port of the memory core that is a 1-bit wide "std_logic_vector" type. Most simulators and HDL synthesis tool will not accept the connection of the two different signal types "std_logic" to "std_logic_vector", although they are the same bit width.


In the Block Memory Generator Core, the width of the write enable input signals (WEA, WEB) might vary depending on the configuration. The width of the write enable buses are larger than 1-bit only if the byte write enable feature is used. To accommodate this, the write enable signal is always a bus of type "std_logic_vector" instead of "std_logic" in VHDL, even when the width of the signal is 1-bit.

When migrating from the Single Port (SP) Block Memory or Dual Port (DP) Block Memory cores to the Block Memory Generator, be aware that the WEA/WEB inputs in the legacy SP and DP cores are of type std_logic, whereas the WEA/WEB inputs of the Block Memory Generator are of type std_logic_vector. This change requires that you use a different method to connect the WEA/WEB inputs to the rest of your design when the write enable is only 1 bit wide.

To connect the WEA port, follow the recommended method:
1. Declare an intermediate signal of type std_logic_vector for the write enable. This will be the signal that will connect to the Block Memory Generator WEA port in the instantiation.
signal we_int : std_logic_vector(0 downto 0);

2. Assign your write enable input (of type std_logic) to bit 0 of the 1-bit-wide intermediate signal.
signal <user_wea>: std_logic;
we_int(0) <= <user_wea>;

3. Connect the intermediate signal you created and assigned during your instantiation of the Block Memory Generator to the WEA port of the core.
user_bmg : bmg_inst PORT MAP (
WEA => we_int;
...other port connections...

This change in WEA/WEB type does not impact customers using Verilog.

A full example instantiation of the Block Memory Generator core is shown below:

signal we_int : std_logic_vector(0 downto 0);
signal <user_wea>: std_logic;
we_int(0) <= <user_wea>;

--Instantiate the new BMG core
uut: blk_mem_gen_v2_2
port map (
dina => <user_dina>,
wea => we_int,
addra => <user_addra>,
ssra => <user_ssra>,
douta => <user_douta>,
clka => <user_clka>,
ena => <user_ena>

This issue is automatically resolved if you run the Block Memory Core Migration Kit available at:

AR# 24048
Date Created 09/28/2006
Last Updated 10/02/2006
Status Active
Type General Article