8.2i EDK SP2 - FSL_V20 Core fails when I select FIFO depth of four.

AR#	24054	Search For Another Answer
Topic	IP-Processor
Last Updated	10/09/2006
Status	Active

Description

Keywords: FSL, processor IP, fsl_v20_v2_00_a, size

There is no advantage to setting the FIFO depth <16 because the same number of LUTs are used for FIFO less than 16. The documentation and MPD will be fixed to only allow the following sizes:

RANGE = (0,16:C_ASYNC_CLKS*128 | !C_ASYNC_CLKS*8192)

Solution

The data sheet and MPD file will be updated in a future release to indicate support of a minimum FIFO size of 16. Currently, the minimum FIFO size supported is 16 (i.e. PARAMETER C_FSL_DEPTH = 16).