8.2i EDK SP2 - MCH OPB DDR2 controller cannot meet 266 MHz timing constraint for slower device in Virtex-5 family (V5 speed grade -1)
Description
Keywords: Virtex-5 timing, processor IP
There is a Virtex-5 speed grade-1 device Fmax limitation. The MCH OPB DDR2 controller cannot meet the 266 MHz timing constraint for slower devices in the Virtex-5 family. Are there any tips or a way to work around this issue to help me improve timing?
Solution
The following are some ways to help you meet timing for the MCH OPB DDR2 controller on the Virtex-5 platform. These suggestions assume that you are using the latest EDK 8.2i SP2 release.- Ensure that you have set all applicable speed-related options in your synthesis and implementation tool. For example, in synthesis you can set optimization mode as speed rather than area to improve the performance. The available options for synthesis and implementation are available in the NGDBuild, MAP, and PAR help files. To view the available options, enter ngdbuild/map/par at the DOS/Unix prompt.
- Critically evaluate your code, and check to see if it is affecting the timing for the MCH OPB DDR2 controller.
- Evaluate the constraints on your core to ensure that each one is both reasonable and necessary. Identify any false paths or multi-cycle paths in your design that cause sections of the design to be treated more loosely by the tools.
- Increase your PAR effort level to High, so that the tool will spend more time on optimizing the algorithms.
- If your design fails to meet the timing requirement by 5-10%, try multi-pass Place and Route (MPPR) or the Xplorer tool.
- If your design fails to meet the timing requirement by 1%, try re-entrant routing.
- If your design still fails to meet the timing, consider the following options:
-- A more powerful synthesis tool.
-- A faster part (higher speed grade).
-- A larger part (e.g., moving from XC5VLX50 to XC5VLX100, then adjusting the amount of pipelining and parallelism).