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AR# 24056

ModelSim (MXE) - Modelsim Xilinx Edition supports only a single HDL Simulation


When I try to simulate a project from ISE , the following error message occurs in ModelSim

"Error Message:


# Loading work.<top_design>(behavioral)

# XE version supports only a single HDL

# Error loading design

# Error: Error loading design

# Pausing macro execution"


If your project is a mixed VHDL/Verilog project, the only way to solve the problem is by changing the simulator; this is a limitation of MXE.

If the source code includes only a single HDL, double check the following options:

- ensure the simulator is selected correctly (MXE VHDL or MXE Verilog)

- when generating the simulation model, select the correct target language

- if your project is purely VHDL code and you are using CORE Generator or Architecture Wizard, check the default language for the HDL functional model by checking the properties in ISE; set it to VHDL

For more information on MXE, see the FAQs in (Xilinx Answer 24506).

AR# 24056
Date 12/15/2012
Status Active
Type General Article