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AR# 24076

MPMC2 - Issues arising from erroneous ISPLB/DSPLB access to unaddressed regions of memory


In order to minimize latency and maximize system bandwidth, it is possible to implement a MPMC2 system with direct point-to-point connections between both Instruction and Data side PLB connections of the PowerPC and the MPMC2.

One of the considerations of doing this is that there is no PLB arbiter on the ISPLB and DSPLB buses. In the scenario where a software application running on the PowerPC attempts to access address space or region which is not being decoded by any device, a deadlock scenario can occur. This deadlock would traditionally be resolved by the arbiter, eventually causing a bus error.

This deadlock has also been observed when using some third party debuggers, when invalid memory reads are attempted.


Solution 1: Add arbitration to the PLB Buses

By replacing the PLB_M1S1 bus with a PLB_v34 bus, the arbiter will be included, and a bus error would occur in the case of an erranous bus transaction.

Solution 2: Entirely cover processor address space

By careful design, the user can entirely fill the PLB addressable space, to ensure that all addresses are either

(a) Responded to by the MPMC2 due to being in the address range of the memory

(b) Bridged to an OPB or PLB PIM - These buses will have bus arbiters, and so un-claimed bus transactions would be propogated back to the PowerPC as a bus error.
AR# 24076
Date Created 10/06/2006
Last Updated 11/12/2010
Status Archive
Type General Article