We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 24098: 9.1i ISE Simulator (ISim) - Known Issues with ISE Simulator
9.1i ISE Simulator (ISim) - Known Issues with ISE Simulator
This Answer Record contains all the Known Issues for ISE Simulator 9.1i.
Q1. When running a design for 60 seconds or more of simulation time, ISE seems to freeze up and hang. Why does this occur?
A1. This has been improved. Now ISE no longer hangs, and instead it issues an out of memory error. This problem will be addressed in the future releases of ISE Simulator.
Q2. When I type "help" and "HELP," I receive different results in the ISE Simulator console window.
A2. This is a known issue with TCL in the Windows Operating System environment. The TCL interface in the simulation console supports simulation commands as well as all valid System Environment commands, such as HELP. Therefore, "HELP" will access the Windows System help command, and "help" will access the ISE Simulator help. There is no fix scheduled for this issue.
Q3. When stepping through the code in the console window, the focus changes from the console window to the HDL Editor window as a new file is opened.
A3. This is currently a limitation of the ISE Simulator. To work around this issue, either use the step button (see ISE Simulator help for details), or click back to the main console window as needed. This issue will be addressed in the future releases of ISE Simulator.
Q4.Signal ordering is not retained in the simulation waveform window after re-entering ISE.
A4.This issue is currently under investigation.
Q5. ISE Simulator is not optimized to be a structural simulator, and this is why some structural netlists (Post-translate/post-MAP/post-PAR) can cause the simulator to hit its maximum limits during compilation.
A5. One way to fix this is to maintain hierarchy in the netlist. Refer to the Synthesis and Simulation Guide for more information, which can be found at: