UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24107

LogiCORE 3GPP Turbo Decoder v2_0 and V3_0 - When I select the ND input, why do I receive decoding errors?

Description

Why, when using the optional input signal ND, do I receive decoding errors?

Solution


There is a new requirement for the ND (New data) signal and the RFD (Ready for Data) signal.  
 
ND must be held High for the next two consecutive clock cycles following RFD being deasserted. That is, ND must be held High for blocksize + 8 clock cycles. The positioning of the extra 2 ND pulses is critical - ND must be held High for the next two active clock cycles following RFD being deasserted. 
 
 
Please see (Xilinx Answer 30166) for a detailed list of LogiCORE 3GPP Turbo Convolutional Code Decoder Release Notes and Known Issues.
AR# 24107
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article