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AR# 2411

COREGEN: Latency of the 4K Area-Optimized Multiplier core


General Description:

The variable multiplier is pipelined several times in order to
enable it to run at high frequencies. The latency that
results from pipelining is a function of the width of the B


The Data is buffered on the input and output of the multiplier
cores. The total latency (number of clocks required to get the
first output) is a function of the width of the B variable
only. The values below presume that both inputs and outputs
are registered.

Width of B input data Latency (# of clocks)

6 to 8 bits 4 clocks
9 to 16 bits 5 clocks
17 to 32 bits 6 clocks
AR# 2411
Date Created 08/21/2007
Last Updated 05/08/2014
Status Archive
Type General Article