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AR# 24114

9.1i CORE Generator - "WARNING:Sim:NetListWriters - The output generated using -ecn option when targeting Virtex-5 currently does not create a simulatable formal verification netlist"

Description


When generating an IP core for a Virtex-5 device with the Formal Verification option selected, the following message occurs:



"WARNING: Sim :NetListWriters - The output generated using -ecn option when targeting Virtex-5 currently does not create a simulatable formal verification netlist. Virtex-5 support will be added in a later release"

Solution


Selecting the Formal Verification option requires CORE Generator to run NetGen with the -ecn option in order to create a Formal Verification netlist for the generated IP core.



NetGen supports formal verification for other device families; however, it is not yet available for Virtex-5. Although NetGen, with the -ecn option, will successfully complete and write out a netlist for Virtex-5, formal verification with this netlist is not possible. The formal verification library for Virtex-5 has not yet been finished with complete functional models for all components. At this stage, the Virtex-5 library uses black box for most of the new components. This causes RTL2gate failure as formal verification requires the functional models to be present in the library. For this reason, the Formal Verification flow with Virtex-5 is temporarily unavailable. The flow will be available for Virtex-5 projects when the libraries have been finished with complete functional models.



The same warning is displayed when the completed design is converted to a netlist.



The library can be used for gate-to-gate verification.



The issue described above is fixed is ISE 9.2i; Formal Verification for Virtex-5 is supported starting with ISE 9.2i.
AR# 24114
Date Created 09/04/2007
Last Updated 07/28/2010
Status Archive
Type General Article