For MIG v2.0 Virtex-4/-5 DDR1/DDR2 SDRAM controllers, what is the correlation between the Address and Data FIFOs on the MIG user interface?
Is there a recommended data phase at which I should load the address into the Address FIFO?
Starting with the MIG 2.1 release, this information is available in the MIG User Guide. Please see the MIG User Guide for further information.
There is a worst-case two-cycle latency from the time the address is loaded into the address FIFO on APP_AF_ADDR[35:0] to the time the controller decodes the address. Because of this latency, it is not necessary to provide the address on the last clock where data is entered into the data FIFO. If the address is written before the last data phase, the overall efficiency and performance increases because it eliminates or reduces the two-cycle latency. However, if the address is written before data is input into the data FIFO, a FIFO empty condition might result because the Data FIFO does not contain valid data.
Based on these considerations, Xilinx recommends entering the address into the address FIFO between the first data phase and the second to last data phase. For a burst of four, this means the Address should coincide with the first data phase. For a burst of eight, the address should be entered two clocks earlier than the last data phase. This implementation increases efficiency by reducing the two clock latency and guarantees that valid data is available in the Data FIFO.