We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24164

8.2i Timing Analyzer/Speed Files - "WARNING:Timing:3233 - Timing Constraint <...> fails the minimum period check ..."


When implementing my design, I receive the following warning:

"WARNING:Timing:3233 - Timing Constraint "NET "clk_400MHz" PERIOD = 2.5 ns HIGH 50%;"

fails the minimum period check for the input clock clk_400MHz to DCM DCM_inst because the period constraint value (2500 ps) is less than the minimum internal period limit of 3332 ps. Please increase the period of the constraint to remove this timing failure."

--even though the DCM is set to Maximum Speed (MS) and High Frequency Mode and only DLL outputs are used on a Virtex-4 device (-10 speed grade).


Currently, the tools use the more restrictive period check for the DFS outputs, which is 3332 ps or 300 MHz for a -10 speedgrade.

If the input and output frequencies coincide with the specification of the "DCM and PMCD Switching Characteristics" in the "Virtex-4 Data Sheet, DC and Switching Characteristics"

these warnings can be ignored.

AR# 24164
Date Created 09/04/2007
Last Updated 01/18/2010
Status Archive
Type General Article