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AR# 24165

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v8.0 - Modifying LOC constraints for Virtex-5 GTP transmit signals

Description

Virtex-5 LXT ES silicon requires transmit signals between the fabric and GTP to be registered and locked down in order to meet timing. The example design ucf provides LOC constraints for a 5VLX50T GTP_DUAL_X0Y2. If a different device or GTP will be used, then refer to the below steps for how to generate the correct constraints.

Solution

Solution A

1. All signals going from FPGA fabric into GTP need to be registered and locked down. The following UCF syntax from the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v8.0 example design ucf file shows which signals they are:

#***********************************************************

# fabric to GTP constraints for the core attached to GTP 0 *

#***********************************************************

# Please align with your chosen GTP (the following are for

# GTP_DUAL_X0Y2 GTP0 in the 5vlx50t device).

# Slice locations for any GTP in any part can be obtained

# by running the GTP RocketIO Wizard

INST "core_wrapper/rocketio/txchardispmode0_reg" LOC = "SLICE_X58Y57";

INST "core_wrapper/rocketio/txchardispval0_reg" LOC = "SLICE_X58Y57";

INST "core_wrapper/rocketio/txcharisk0_reg" LOC = "SLICE_X58Y57";

INST "core_wrapper/rocketio/txdata0_reg_0" LOC = "SLICE_X58Y56";

INST "core_wrapper/rocketio/txdata0_reg_1" LOC = "SLICE_X58Y56";

INST "core_wrapper/rocketio/txdata0_reg_2" LOC = "SLICE_X58Y56";

INST "core_wrapper/rocketio/txdata0_reg_3" LOC = "SLICE_X58Y56";

INST "core_wrapper/rocketio/txdata0_reg_4" LOC = "SLICE_X59Y56";

INST "core_wrapper/rocketio/txdata0_reg_5" LOC = "SLICE_X59Y56";

INST "core_wrapper/rocketio/txdata0_reg_6" LOC = "SLICE_X59Y56";

INST "core_wrapper/rocketio/txdata0_reg_7" LOC = "SLICE_X59Y56";

2. To generate constraints for other parts and other GTPs, run the RocketIO GTP Wizard in CORE Generator with the correct target device. Leave all of the options as the default except:

-On page 1, choose the GTPs that will be used.

-On page 2 of the RocketIO GTP Wizard, select:

silicon: ES

targetline rate: 1.25 Gbps

refclk: 125

protocol template: gigabit ethernet

-On page 3 of the RocketIO GTP Wizard, check the boxes for:

TXCHARDISPMODE

TXCHARDISPVAL

3. The output will contain the constraints embedded into the GTP wrapper code in: <coregen_project>/<core_name>/src/<corename>.v (vhd). The location constraints provided in this file will need to be used to replace the ucf constraints above.

For example, here is a section from this file. Although not exact, there is a close correspondence in the naming:

*************************** MAXDELAY and LOC constraints ********************

attribute loc : string;

attribute maxdelay : string;

attribute loc of tile0_txdata0_r_0_i : label is "SLICE_X58Y56";

attribute loc of tile0_txdata0_r_1_i : label is "SLICE_X58Y56";

attribute loc of tile0_txdata0_r_2_i : label is "SLICE_X58Y56";

attribute loc of tile0_txdata0_r_3_i : label is "SLICE_X58Y56";

attribute loc of tile0_txdata0_r_4_i : label is "SLICE_X59Y56";

attribute loc of tile0_txdata0_r_5_i : label is "SLICE_X59Y56";

attribute loc of tile0_txdata0_r_6_i : label is "SLICE_X59Y56";

attribute loc of tile0_txdata0_r_7_i : label is "SLICE_X59Y56";

attribute loc of tile0_txchardispmode0_r_0_i : label is "SLICE_X58Y57";

attribute loc of tile0_txchardispval0_r_0_i : label is "SLICE_X58Y57";

attribute loc of tile0_txcharisk0_r_0_i : label is "SLICE_X58Y57";

Solution B

The location constraints can also be manually calculated.

1. If staying in V5LX50T, the X-coordinate will stay the same for all GTP locations. If targeting a V5LX110T, the X-coordinate 58 should be replaced with 106 and the X-coordinate 59 should be replaced with 107.

2. To move up one GTP_DUAL location, add 20 to the Y-coordinates. To move down one GTP, subtract 20 from the Y-coordinates.

AR# 24165
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article