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AR# 24217

14.x Timing - Jitter Information Master Record


Where can I find information about jitter?


What are the different types of Jitter reported as uncertainty? See (Xilinx Answer 37430).

How is jitter included in Timing Analysis? See (Xilinx Answer 23710).

Where is information on output jitter on PMCD? See (Xilinx Answer 21446).

Where is information on output jitter on DLL/DCM? See (Xilinx Answer 13645).

How can I set the jitter for CLK0 and CLKFX separately (uncertainty)? See (Xilinx Answer 20828).

Where is information on setting output jitter for different DLL/DCM/PLL taps? See (Xilinx Answer 20828).

Why is my PLL Jitter lower than my System Jitter? See (Xilinx Answer 32631).

How to calculate System Jitter (Xilinx Answer 39898)

How is total system jitter (TSJ) calculated for any particular device? (Xilinx Answer 37702)

How to convert Oscillator Phase Noise to Time Jitter? (Xilinx Answer 35940)

How is clock uncertainty being calculated now that DCM jitter and phase error have been characterized for Virtex-4 (and newer) devices? (Xilinx Answer 23710)

How can I set the jitter for CLK0 and CLKFX separately (uncertainty)? (Xilinx Answer 20828)

How can the SYSTEM_JITTER constraint be used? (Xilinx Answer 24518)
AR# 24217
Date Created 09/04/2007
Last Updated 05/16/2012
Status Active
Type Known Issues
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
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  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
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  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
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