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AR# 24219

12.1 Timing - Why is my clock path delay different between OFFSET IN and OFFSET OUT constraints?

Description

Why is my clock path different in the OFFSET IN analysis as compared to the OFFSET OUT analysis?

Solution


The OFFSET IN analysis performs a setup analysis on the data and clock paths. To obtain a worse-case value for setup and hold, the timing tools should use a "minimum" clock path for setup calculations and a "minimum" data path for hold calculations.
I/O Setup = Data Path Delay(max) + FF Setup - Clock Path Delay(min)
I/O Hold = Clock Path Delay(max) + FF Hold - Data Path Delay(min)
Internal Hold = Data Path Delay(min) - Clock Skew
These two equations generate more accurate timing values for I/O setup and hold times and internal hold analysis.
Problems with a max-max calculation for I/O timing have not always been obvious because a failure occurs only when the upstream devices are the absolute fastest, and the downstream device is the absolute slowest; this situation rarely occurs in the field.
However, in most current designs the I/O limits are being pushed. Consequently, source synchronous timing techniques (i.e., clock and data are traveling together with a data valid window of 1.5 ns) are used in current designs. Consequently, the timing tools must be more accurate in the I/O setup and hold analysis.
For better accuracy in the I/O setup and hold analysis, the timing tools must use a min-max calculation instead of a max-max calculation. What is the minimum value? The timing tools can use zero, but this is too conservative for customer designs. The timing tools can use the absolute minimums, as they are available for most of the Xilinx device families. This is also too conservative, as the device cannot be at the two extremes (temperature, process, and voltage) at one time. To resolve this question, Xilinx developed a new terminology, called Relative Minimum, which describes the correct minimum value when compared to the maximum value.
Relative Minimum values are meaningful only when compared to a maximum value. If a data path is at the maximum delay, how fast can the clock be when calculating the setup time? The relative minimum is a factor of the maximum value, which is based on characterization of the device family. These values are used in the I/O setup and hold calculations, and internal hold calculation, as noted previously. These factors are typically 85% for global resources (BUFGMUX, Global Clock Routing) and typically 80% for local resources (everything else) on Virtex-II Pro, Spartan-3, and new device families.
You can use the "speedprint" command to determine whether the current speed files include Relative Min Data. The relative minimum data in the speed files were introduced in ISE 5.2i SP2.
The OFFSET OUT analysis provides the worse-case values for both data and clock paths. The same clock path is used in both the OFFSET IN and OFFSET OUT analysis, but the OFFSET IN clock path is the relative minimum value.
For more information, see (Xilinx Answer 21327) and (Xilinx Answer 5489)
AR# 24219
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • Less