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AR# 24221

14.x Timing - Understanding the data sheet style section of the timing report

Description

What is the data sheet style section of the timing report?

Solution

The data sheet section numbers are created from a timing analysis against constraints. It provides numbers for I/Os setup/hold, clock to out, and other external data sheet numbers. The data sheet style section of the timing report provides an external perspective of the design for board analysis.

The -u (unconstrained paths) switch will pick up any unconstrained I/Os, and the use of Advanced Analysis (Auto-generated constraints) or default analysis will pick up I/O timing.

The report includes the source and destination PAD names, and either the propagation delay between the source and destination or the setup and hold requirements for the source relative to the destination.

This report summarizes the following delay characteristics for the design:

Reporting of External Setup/Hold Requirements

The maximum setup and hold times of chip data inputs are listed relative to each clock input. When two or more paths from a data input exist relative to a chip clock input, the worse-case setup and hold times are reported. One worse-case setup and hold time is reported for each data input and clock input combination in the design. This section accounts for clock phase relationships and DCM phase shifting for all derivatives of a primary clock input, and reports separate data sheet setup and hold requirements for each primary input relative to all derivatives of a primary clock input covered by a timing constraint. This section reports separate setup and hold requirements for user-defined internal clocks. User-defined external clock relationships are reported separately.

Clock-to-Clock Setup/Hold Requirements

The maximum setup and hold times for synchronous-to-synchronous elements are listed for each clock. The data sheet section for Clock-to-Setup by clock destination reports clock information by clock pad. This means that clocks distributed by a DLL/DCM are reported only by the clock pad. For example, if a clock (clk) drives the clk_in of a DLL/DCM, and the DLL/DCM outputs both 0 phase (clk0) and div2 (clkdiv2) clocks, the table in the data sheet will include all information from those two distributed clocks. The clock arrival time will be included in the Clock-to-Setup to clock destination table.

Suppose "clk" has a period of 10 ns (50% duty cycle) and "clkdiv2" has a rising-to-falling minimum of 8 ns. The 8 ns half cycle is acceptable, as that is less than half of the clkdiv2 period; however, it appears in the data sheet section as 8 ns in the clk Clock-to-Setup table, which appears to be a violation of the 10 ns half cycle value of 5 ns. The same will be true of a rising-to-rising value for clkdiv2, which can be twice as large as the clk requirement.

Reporting of Clock-to-Output Propagation Delays

The maximum propagation delay from clock inputs to chip data outputs is listed for each clock input. When two or more paths from a clock input to a data output exist, the worse-case propagation delay is reported. One worse-case propagation delay is reported for each data output and clock input combination.

Reporting of Input-to-Output Propagation Delays

The maximum propagation delay from each chip input to each chip output is reported if a combinational path exists between the chip input and output. When two or more paths exist between a chip input and output, the worse-case propagation delay is reported. One worse-case propagation delay is reported for every input and output combination in the design.

OFFSET IN Bus Requirement

Each OFFSET IN constraint with a user-specified offset value and non-zero duration generates one OFFSET IN Bus Table. An OFFSET IN Bus Table includes a summary and a table. The summary includes the constraint name, the worse-case data valid window, and the offset of the ideal clock to the actual clock. The offset of the ideal clock to the actual clock is the adjustment needed to center the actual clock given the current bus setup and hold requirements. The table lists data input signals and statistics. Each data input signal is listed in one or two row entries; one for rising-edge triggered synchronous elements and one for falling-edge triggered synchronous elements.

If a data input signal has multiple rising-edge triggered destinations or multiple falling-edge triggered destinations, the worse case, that is, the smallest, value, is used. Each row includes column entries for the source name, setup time, hold time, setup slack, hold slack, and offset of the source's data window to the specified offset data valid window. The offset of the source's data window to the specified offset data valid window can be used to center the source's setup and hold slack within the specified offset data valid window.

The source name matches that found in the verbose report. The setup slack and hold slack are calculated in the same manner and match the verbose report listing for this input. The data window is equal to the setup slack plus the hold slack. The center adjustment is equal to the amount of additional delay that, when added to the data path, would cause the clock to be centered for this input.

Pad-to-setup Requirement

The external setup time between a design data input pad and a clock input pad is calculated as the maximum path delay from the data pad to a register plus the maximum setup time of the register, less the minimum of maximum path delay(s) from the clock pad to the register. If the data input has two or more internal setup requirements relative to the same external clock, the worse-case setup times are calculated.

Pad-to-hold Requirement

The external hold time between a data input pad and a clock input is calculated as the maximum path delay from the clock pad to a register plus the maximum hold time of the register, less the minimum of maximum path delay(s) from the data pad to the register. If the data input has two or more internal hold requirements relative to the same external clock, the worse-case hold times are calculated.

Clock-to-pad Propagation Delay

The clock-to-pad propagation delay is calculated as the sum of the maximum clock-to-register delay, the register's clock-to-output delay (typically Tcko), and the maximum register-to-pad delay.

Pad-to-pad Propagation Delay

The pad-to-pad propagation delay is calculated as the sum of the maximum path delay constituents from the input pad to the output pad.

Also, see (Xilinx Answer 21328)
AR# 24221
Date Created 09/04/2007
Last Updated 11/14/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
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  • ISE Design Suite - 12.4
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