The Virtex-5 System Monitor simulation model shows issues where the behavior does not accurately reflect the hardware.
In the existing model, the sequencer mode conversion time was incorrect. In addition, if changes were made to the configuration of the System Monitor during operation, the changes were applied immediately, which is not accurate.
These issues have been fixed in a new model that will be included in the ISE 9.1 release of the software. In the meantime, the files can be downloaded for use with ISE 8.2.3.
The files included in this patch are enhancements to the System Monitor behavioral simulation models only. These enhancements are supported only for simulators that do not use pre-compiled libraries (such as ISIM and ModelSim XE).
The files can be downloaded from the following location:
For Verilog users :
Overwrite the "sysmon.v" file in the "Xilinx\verilog\src\unisim" directory.
For VHDL users :
Overwrite the "unisim_VITAL.vhd" in the "Xilinx\vhdl\src\unisims" directory.
Once the files are saved, you must recompile the simulation libraries using CompXLib for the changes to take effect.
For instructions on how to compile your libraries, see (Xilinx Answer 15338).
If you have any questions regarding the post-PAR simulation models, please contact Xilinx Technical Support for assistance: