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AR# 2424

FPGA Configuration 4000/5200 - Performing readback/verification of FPGA configuration

Description

General Description:

An FPGA can output the state of its configuration memory and the state of its flip-flops, RAMs, and IOBs through a process called Readback.

How do I set up and design my XC4000 or XC5200 FPGA to perform Readback?

Solution

1. The 'Readback' symbol must be instantiated in your schematic or DL description.

- Connect the Data pin to an 'OBUF' symbol which should be connected to an 'OPAD' symbol.

- Connect the CLK pin to an 'IBUF' symbol which should be connected to an 'IPAD' symbol.

- Connect the TRIG pin to an 'IBUF' symbol which should be connected to an 'IPAD' symbol.

- You can optionally connect the RIP pin to an 'OBUF' symbol which should be connected to an 'OPAD' symbol.

The Readback data is serially outputed on the rising edge of the CLK.

A Readback is initiated by a low-to-high transition on the TRIG pin, and a high-to-low transition on the TRIG pin can optionally abort a Readback. The RIP pin can optionally be used to monitor if a Readback is in progress.

2. You must set some options in makebits (XACT 6.0.1 software) or BitGen (M1 software) to enable Readback.

- Set the '-f ReadCapture:Enable' option to enable the FPGA to perform readback.

- Set the '-f ReadClk:Rdbk' option to specify the use of a user-defined clock for readback (recommended). If the CLK pin on the READBACK symbol is left unconnected *AND* this option is set to '-f ReadCLK:CCLK' , then the internal CCLK will be used to clock the readback data.

- Optionally set '-f ReadAbort:Enable' if you want to be able to abort a readback while the data is being read out.

NOTE: For BitGen, you must use -g instead of -f.

3. The readback bitstream will contain two kinds of data: configuration bits and state bits. Configuration bits reflect the programmed logic and interconnect, and they should remain static as the device operates. The state bits represent the states of internal flip-flops, RAMs, and IOBs; these bits change as the device operates. By comparing the configuration bits in the readback bitstream with the configuration bits in the download bitstream, you can determine whether the configuration logic has changed; this can happen, for example, in radioactive environments. By examining state bits, you can determine the value of a signal internal to the FPGA.

4. To decode a readback bitstream, you can use a Logic Allocation file (.ll) or a Mask file (.msk).

A Logic Allocation file is an ASCII file that lists the bit positions of all the state bits. It also shows the assignment between signal names in your design and the state bits. A Logic Allocation file is used for probing internal signals.

A mask file is a binary file that is structurally equivalent to a Readback bitstream. If a particular bit, for instance, bit 538, has a 0 in the mask file, this indicates that bit 538 in the readback bitstream is a configuration bit. The mask file is used for verifying that the configuration memory has not changed.

- To generate the Logic Allocation file, use the '-l' option with either makebits or BitGen.

- To generate the Mask file, use the '-m' option with either makebits or BitGen.

For more information on Readback for XC4000 or XC5200 family of devices, see the Xilinx Application Note XAPP17: "Using the XC4000 Readback Capability," page 1.

http://direct.xilinx.com/bvdocs/appnotes/xapp017.pdf

AR# 2424
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article