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AR# 24244

MIG 1.6 - "ERROR:Place:311 - The IOB cntrl0_DDR2_DQS is locked to site IOB_X1Y143 in bank 12. This violates the SelectIO banking rules."


When using the pin-out from MIG 1.6, PAR reports the following error:

"ERROR:Place:311 - The IOB cntrl0_DDR2_DQS[0] is locked to site IOB_X2Y143 in bank 12. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site."


The UCF generated by MIG 1.6 sets DQ bits to SSTL18_DCI and DQS bits to DIFF_SSTL18_DCI. In some versions of ISE, PAR incorrectly flags DQ and DQS as having different I/O standards. This does not occur in all versions of ISE.

To work around this issue, you can:

1. Remove the DCI option in the UCF for DQ and DQS.

2. Then rerun the design through PAR.

3. After PAR completes successfully, open FPGA Editor and turn DCI back on manually in the IOBs.

4. To do this, highlight the IOB of interest in the "List" window.

5. Click the "Zoom Selection" icon to zoom into the IOB.

6. Double-click the IOB to open the block.

7. Next, ensure you are in "Read Write" mode (noted at the bottom right of the window). If you are not in "Read Write" mode, select "EditMode" in the far right column.

8. Next, select "EditBlock" from the far right column.

9. This will allow you to change the I/O standard by double-clicking the I/O Standard of interest.

10. Save the changes.

This error can also occur if the differential declaration on the DQS bits is removed. Ensure that the DIFF_ prefix is retained on differential signals.

This is resolved in ISE 9.1i Service Pack 1.
AR# 24244
Date 03/30/2012
Status Archive
Type General Article
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