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AR# 24278

8.2.03i Netgen - Timing Simulation - Virtex-5 Simulation netlist contains TIEOFFREGCEAL pin for FIFO18_36, which causes the simulation to fail

Description

Keywords: Virtex-5, FIFO, Pin, FIFO18_36

Virtex-5 Simulation netlist contains TIEOFFREGCEAL pin for FIFO18_36, which causes the simulation to fail. How do I fix it?

Solution

Please open a WebCase with Xilinx Technical Support at: http://www.xilinx.com/support/clearexpress/websupport.htm to receive a solution for this issue.

This issue is fixed in ISE 9.1i



AR# 24278
Date Created 09/04/2007
Last Updated 11/17/2008
Status Archive
Type General Article