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AR# 24284

8.2i SimPrim - Virtex-5 Embedded TEMAC RGMII mode fails timing when EMAC#_RGMII_ENABLE attributes are set to TRUE


When the EMAC#_RGMII_ENABLE attributes are set to TRUE, the top four bits of the PHY side data (PHYEMAC#RXD[7:4] / EMAC#PHYTXD[7:4]) and error signals (PHYEMAC#RXER / EMAC#PHYTXER) are clocked on the falling edge in the TEMAC hard block. The generated simulation model treats these inputs and outputs as clocked on the rising edge, which can invalidate timing errors because the simulation only gives the path half as much time as it actually needs to reach (or come from) the falling-edge clocked registers in the fabric.


Open a WebCase with Xilinx Technical Support for a solution: http://www.xilinx.com/support/clearexpress/websupport.htm

This issue is scheduled to be fixed in the next major release of the design tools.

AR# 24284
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article