Why does the OutputRDY signal remain High for six clock cycles after the output FIFO is empty? How is the data on the output of the TPC validated?
The OutputRDY signal remains High for six clock cycles because of internal pipeline delays related to how the signal was generated. The procedure for reading data from the decoder is as follows:
1. Check that the OutputRDY signal goes active High.
2. Assert "Outputen" signal for the number of clock cycles dependent on the code rate and the OutputRDY being High.
The number of clock cycles depends on the code rate. For example, for a (32,26) code, 256 clock cycles are required. This number is obtained from 32^2 = 1024 bits produced by the decoder; however, since these are produced four at a time, this results in 256 clock cycles needed to empty the code block.
For a detailed list of LogiCORE Turbo Product Code (TPC) Decoder Release Notes and Known Issues, see (Xilinx Answer 30178).