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AR# 24326

9.1i EDK - plb_ddr2_v1_01_a: Implementing plb_ddr2 controller with EDK 8.2i SP2 results in timing error

Description


I created my design with Base System Builder, and implemented it. The tool reports that the timing is not met:



CONSTRAINT

TS_dcm_0_dcm_0_CLK2X_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLK2X_BUF" TS_sys_clk_pin / 2 HIGH 50%



REQUESTED -> 5.000ns

ACTUAL -> 6.026ns

LOGIC LEVELS -> 0

ABSOLUTE SLACK -> -1.026ns

Solution


This problem has been fixed for the plb_ddr2_v1_02_b in the latest EDK 9.1i Service Pack, available at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 9.1i Service Pack 2.
AR# 24326
Date Created 09/04/2007
Last Updated 04/26/2011
Status Archive
Type General Article