We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24327

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v8.0 - Incorrect signal name used in Virtex-5 SGMII Verilog example design wrapper


For Virtex-5 LXT Verilog SGMII designs, a typo must be corrected in the "<component_name>_block.v" example design wrapper file. This is not a problem if using VHDL.


The file "<component_name>_block.v" can be found in the "<component_name>\example_design" directory. 


This is the current code in the instantiation of the "sgmii_adapt" module: 


.speed_is_10_100 (speed0_is_10_100_reg), 

.speed_is_100 (speed0_is_100_reg) 


This should be changed to: 


.speed_is_10_100 (speed0_is_10_100), 

.speed_is_100 (speed0_is_100) 


That is, remove the "_reg". 


This will be fixed in version 8.1 of the core scheduled to be released in 9.1i IPUpdate1, which is scheduled to be out in February 2007.

AR# 24327
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article