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AR# 2435

12.1 Timing Closure - Zero (0) or fewer than expected paths or items are analyzed for a TIMESPEC that should apply to valid paths in my design

Description

Timing Analyzer reports that it analyzed zero (0) or fewer than expected paths or items for a TIMESPEC that should apply to valid paths in my design.

Solution

Generally, three different situations could cause this issue:

  • Multiple timing constraints in the design are overlapping, causing some constraints to take precedence over others.
  • All or some of the paths covered by one constraint are also covered by other, high-priority constraints, completely overriding the original constraint.
  • The source or destinations are invalid.

The TIMESPEC Interaction (TSI) Report is useful for determining which paths are covered by particular constraints. The TSI option is available only through Trace (TRCE), on the command line. The following is an example of the command:

trce -tsi the_tsi_report design.ncd design.pcf

AR# 2435
Date Created 08/21/2007
Last Updated 05/15/2012
Status Active
Type Known Issues
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • More
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Spartan-3
  • Spartan-3 XA
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Less