In the device data sheets, there are many timing parameters (for example, FTOGGLE, FSYSTEM, FEXT).
How do you use this information to figure out the maximum frequency your CPLD can be run at?
To be sure that a specific design will met timing, it is strongly recommended the designer does a post fit timing analysis. The constraint file should contain period, offset in, and offset out constraints.
The specifications in the data sheet are for specific elements.
FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle.
FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per
macrocell while FSYSTEM2 is through the OR array.
FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array.
For a specific design, you would need to know the levels of logic and the components that up the levels of logic to determine the maximum frequency.