AR #24421 - Virtex-5 System Monitor - How do I power the System Monitor on a Virtex-5 FPGA?

AR#	24421
Part	FPGA-System Monitor
Last Modified	2008-07-16 00:00:00.0
Status	Active
Keywords	V-5, V5

Solution

See the Virtex-5 System Monitor User Guide (UG192) for information on this issue:

http://www.xilinx.com/support/documentation/virtex-5.htm#19297

To disable the System Monitor, connect AVDD, VREFP, VREPN, and AVSS to ground reference. Also, connect VP and VN to GND.

Can the user deviate from the recommendations?

While any connections other than those recommended have not been fully tested, the following guidelines apply:

- The GND reference pins (AVSS_SM and VREFN) must NOT be tied to any Vcc supply and must be tied to GND. Failure to met this requirement will damage the FPGA. Xilinx cannot support any designs that do not have AVSS_SM and VREFN connected to GND.
- Due to untested and potential latchup/ESD issues, no pin should be left floating. Xilinx has not done any testing with the System Monitor pins left floating. It is not expected that it would damage the device, but due to the untested nature of the setup this cannot be guaranteed.