In the section <The Delay Summary Report>, confusing delays are reported:
The AVERAGE CONNECTION DELAY for this design is: 1.005
The MAXIMUM PIN DELAY IS: 6.194
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.394
Connection and Pin Delay are the same type of thing. They are basically the delays of any routed net in a design.
If you open the design in the FPGA Editor, change to "Nets" in the "List" window, select all nets and click the "delay" button on the right side. You will find the "Max Pin Delay" column populated with delay values. You can then sort this column such that the net with the delay of 6.194 ns is shown at the top. The Maximum pin delay will be the worst delay, and then connection delays will be averages of these delays.