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AR# 24444

LogiCORE Endpoint for PCI Express v3.4 - How to correct link stability issues using 125 MHz REFCLK on PLDA boards


When using PLDA development board for PCI Express with Virtex-4 parts and the supplied reference clock to the MGT is 125 MHz, the link is not training or stable.


Important: Xilinx recommends and supports synchronous clocking schemes, see (Xilinx Answer 18329). Virtex-4 requires a 250 MHz reference clock to abide by the jitter specifications laid out in the PCI Base Specification v1.1. When using 125 MHz clock, first refer to (Xilinx Answer 23407), which lists the values of specific MGT and DCM attributes that must be set.  


Below are suggestions to improve the stability of the link and eliminate packet errors when using a 125 MHz PLDA board: 


1. The first edit should be made to the dividers located in the MGT PLL. To overwrite these attributes, you must make declarations in the UCF. The default values for the PLL dividers are TXPLLDIVSEL = 40 and TXOUTDIV2SEL = 4. Change these values to: 






For example: 


INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST" TXPLLDIVSEL = 20; 

INST "ep/BU2/U0/pci_exp_4_lane_32b_ep0/plm/v4f_mgt/gt11_by4/GT11_PCIEXP_4_INST2" TXOUTDIV2SEL = 2;  


Reducing this value shortens the amount the MGT will wander and increases link stability and cleanliness. However, the minimum you can reduce this to is 20 and 2, due to the bandwidth window on the Voltage Controlled Oscillator within the MGT.  


2. Verify that you are using ES4 parts and that you have the correct stepping level set in the UCF. The syntax is shown below: 



AR# 24444
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article