AR# 24455

10.1 Floorplan Editor, PACE - DRC does not give errors even if assigning outputs differential standards on low capacitance pins on Virtex-4

In the Floorplan Editor/PACE, the following standards can be placed on a low cap (LC) IOB site:

(LVDS_25, LVDSEXT_25, LVDS_25_DCI, LVDSEXT_25_DCI, ULVDS_25, and LDT_25)

This breaks the rules for Differential Termination in the Virtex-4 User Guide. Which one is correct?

There should be DRC errors in Floorplan Editor/PACE. This problem has been fixed in PlanAhead. Please use PlanAhead to have a correct DRC.

For more information about Differential Termination, refer to Chapter 6 of the Virtex-4 User Guide :

http://www.xilinx.com/support/documentation/virtex-4.htm#19324

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