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AR# 24478 Spartan-3E/-3A - The C0 and C1 alignment feature of the ODDR2 flip-flop is not supported

Keywords: Spartan-3A, Spartan-3E, ODDR, ODDR2, DDR_ALIGNMENT, C0, C1, work around

In Spartan-3E and Spartan-3A Engineering Samples (ES), the new ODDR2 flip-flop does not support ALIGNMENT set to C0 or C1. The data sheet includes the following statement:

"Caution! The C0 or C1 alignment feature of the ODDR2
flip-flop, originally introduced in the Spartan-3E FPGA family,
is not recommend or supported in the ISE development
software. The ODDR2 flip-flop without the alignment feature
remains fully supported. Without the alignment feature, the
ODDR2 feature behaves equivalent to the ODDR flip-flop on
previous Xilinx FPGA families."

Is there a way to implement an equivalent functionality to the ODDR2 with C0/C1 alignment?

For all Spartan-3E and ES silicon of Spartan-3A, ODDR2 with DDR_ALIGNMENT set to C0 or C1 is not supported in the software and might result in data corruption when implemented in the hardware. For Production silicon of Spartan-3A, C0 and C1 alignment is fully functional and supported.

Note that when using the ODDR2, the default alignment is DDR_ALIGNMENT=NONE, which is used in the majority of designs. Also, note that IDDR2 fully supports all DDR_ALIGNMENT options.

Below are three possible ways to work around the ODDR2 C0/C1 alignment known issue:

Solution 1: Using ODDR With Alignment=NONE

Use the ODDR2 without the alignment feature. Set DDR_ALIGNMENT=NONE for the ODDR2 flip-flop. The flip-flop still has its full DDR functionality and no data corruption is evident. This implementation uses no extra logic, but is not the same design, logically, as the original. The design must be re-simulated.

Solution 2: Using ODDR With Alignment=NONE (1 extra CLB flip-flop)

As the data sheet states, you must use the ODDR2 flip-flop with DDR_ALIGNMENT=NONE. This allows you to implement alignment in the fabric using a CLB flip-flop and the IOB ODDR flip-flops. This design adds one flip-flop, but is logically identical to the original. Example code is provided below to help implement the design:




Verilog Code:
-------------------------------------------------------------------
FD ff_newa (
.D (d[1]),
.C (clk),
.Q (newa)) ;

ODDR2 #(.DDR_ALIGNMENT("NONE"))
clkout_reg (
.C0 (clk),
.C1 (clknot),
.D0 (d[0]),
.D1 (newa),
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.Q (dout)) ;
-------------------------------------------------------------------

VHDL Code:
-------------------------------------------------------------------
ff_newa : fd port map(
d => d(1),
c => clk,
q => newa) ;

clkout_reg : oddr2
generic map (
DDR_ALIGNMENT => "NONE")
port map (
d0 => d(0),
d1 => newa,
c0 => clk,
c1 => clknot,
ce => '1',
r => '0',
s => '0',
q => dout );
-------------------------------------------------------------------


Solution 3: Using ODDR With Alignment=NONE (3 extra CLB flip-flops)

This solution implements similar functionality to the ODDR2 using alignment, but it uses three CLB flip-flops with the ODDR flip-flops. This adds three flip-flops for the highest possible performance, but also adds one clock cycle to the timing of the original (which is typically not a problem in source-synchronous systems). This solution should be used in designs requiring higher performance. You can reference the following code to implement the setup and help with the necessary floorplanning to achieve higher speeds:




Verilog Code:
-------------------------------------------------------------------
(* RLOC = "x0y0", BEL = "FFY" *) FD ff_newa(
.D (d[1]),
.C (clk),
.Q (newa)) ;

(* RLOC = "x0y1", BEL = "FFX" *) FD ff_newb(
.D (newa),
.C (clknot),
.Q (newb)) ;

FD ff_newc (
.D (d[0]),
.C (clk),
.Q (newc)) ;

ODDR2 #(.DDR_ALIGNMENT("NONE"))
clkout_reg (
.C0 (clk),
.C1 (clknot),
.D0 (newc),
.D1 (newa),
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.Q (dout)) ;
-------------------------------------------------------------------


VHDL Code:
-------------------------------------------------------------------
attribute rloc : string ;
attribute bel : string ;
attribute rloc of ff_newa : label is "x0y0" ;
attribute bel of fd_newa : label is "FFY" ;
attribute rloc of ff_newb : label is "x0y1" ;
attribute bel of fd_newb : label is "FFX" ;

ff_newa : fd port map(
d => d(1),
c => clk,
q => newa) ;

ff_newb : fd port map(
d => newa,
c => clknot,
q => newb) ;

ff_newc : fd port map(
d => d(0),
c => clk,
q => newa) ;

clkout_reg : oddr2
generic map (
DDR_ALIGNMENT => "NONE")
port map (
d0 => newa,
d1 => newc,
c0 => clk,
c1 => clknot,
ce => '1',
r => '0',
s => '0',
q => dout );
-------------------------------------------------------------------


For more information, reference:

The "Spartan-3E FPGA Family Complete Data Sheet (All four modules)" v3.4 (DS312):
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

The "Spartan-3A FPGA Family Data Sheet" v1.0 (DS529):
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

The "Spartan-3 Generation FPGA User Guide" v1.0 Preliminary (UG331):
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides

The Spartan-3A Errata:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Errata
AR# 24478
Date Created
Last Updated 01/28/2007
Status Active
Type