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AR# 2449 12.1 Constraints/Timing - Basic User Constraints File (UCF) syntax examples for design placement and timing constraints

The following is a summary of common User Constraints File (UCF) directives. For a complete description, see the Constraints Guide, accessible from:
http://www.xilinx.com/support/software_manuals.htm

For more information, see (Xilinx Answer 3416), (Xilinx Answer 3753), and (Xilinx Answer 6662).
Basic UCF Syntax Examples for Timing Specifications

PERIOD TIME-SPEC

The PERIOD specification covers all timing paths that start or end at a register, latch, or synchronous RAM that are clocked by the reference net (excluding pad destinations). It also covers the setup requirement of the synchronous element relative to other elements (e.g., flip-flops, etc.).

NOTE: The default unit for time is nanoseconds.

NET clk20MHz PERIOD = 50 ;
NET clk50mhz TNM = registers_50mhz ;
TIMESPEC TS01 = PERIOD registers_50mhz 20 ;

FROM:TO TIME-SPECs

FROM:TO style time specs can be used to constrain paths between time groups.

NOTE: The keywords RAMS, FFS, PADS, and LATCHES are predefined time groups used to specify all elements of each type in a design.


TIMESPEC TS02 = FROM : PADS : TO : FFS : 36 ;
TIMESPEC TS03 = FROM : FFS : TO : PADS : 36 ns ;
TIMESPEC TS04 = FROM : PADS : TO : PADS : 66 ;
TIMESPEC TS05 = FROM : PADS : TO : RAMS : 36 ;
TIMESPEC TS06 = FROM : RAMS : TO : PADS : 35.5 ;


NOTE: The predefined time groups LATCHES and RAMS are not applicable to CPLD designs.


OFFSET TIMESPEC

For more detail on OFFSET, see Xilinx WP237, "What are OFFSET Constraints" at:
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=White+Papers

To automatically include clock buffer/routing delay in your "PADS:TO:<synchronous element> or <synchronous element>:TO:PADS timing specifications, use OFFSET constraints instead of FROM:TO constraints.


For an input where the maximum clock-to-out (Tco) of the driving device is 10 ns:

NET in_net_name OFFSET = IN : 10 : AFTER : clk_net_name ;


For an output where the minimum setup time (Tsu) of the device being driven is 5 ns:

NET out_net_name OFFSET = OUT : 5 : BEFORE : clk_net_name ;


TIMING IGNORE

If the timing of paths can be ignored, use Timing Ignore (TIG).

NOTE: You can use the "*" character as a wild card for bus names. You can use a "?" character as a one-character wild card.


To ignore timing of net "reset_n":

NET : reset_n : TIG ;


To ignore data_reg(7:0) net in instance "mux_mem":

NET : mux_mem/data_reg* : TIG ;


To ignore data_reg(7:0) net in instance "mux_mem" as related to a TIMESPEC named TS01 only:

NET : mux_mem/data_reg* : TIG = TS01 ;


To ignore "data1_sig" and "data2_sig" nets:

NET : data?_sig : TIG ;


PATH EXCEPTIONS

If your design contains outputs that can be slower than others, you can create specific TIMESPECs similar to this example for output nets named "out_data(7:0)" and "irq_n":


TIMEGRP slow_outs = PADS(out_data* : irq_n) ;
TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ;
TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ;
TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ;


If multi-cycle FF-to-FF paths exist, you can create a time group using either the TIMEGRP or TNM statements.


WARNING: Many VHDL/Verilog synthesizers do not predictably name flip-flop Q output nets. However, most synthesizers do assign predictable instance names to flip-flops.


TIMEGRP example:

TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* :
inst_path/ff_q_output_net2*);


TNM attached to instance example:

INST inst_path/ff_instance_name1_reg* TNM = slowffs ;
INST inst_path/ff_instance_name2_reg* TNM = slowffs ;


If an FF clock-enable is used on all flip-flops of a multi-cycle path, you can attach TNM to the clock enable net.

NOTE: TNM attached to a net "forward traces" to any FF, LATCH, RAM, or PAD attached to the net.


NET ff_clock_enable_net TNM = slowffs ;


The following example uses "slowffs" time group, in a FROM:TO TIMESPEC, with either of the three time group methods shown above:

TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ;


Controlling Skew

To constrain the skew or delay associated with a net:

NET any_net_name MAXSKEW = 7 ;
NET any_net_name MAXDELAY = 20 ns;


Priorities

For more information, see (Xilinx Answer 5747).

Please provide feedback on how this Answer Record meet your needs.


Specifying Placement Constraints for Logic or I/O

Assigning or Prohibiting I/O pin numbers

Assigning I/O Pin Numbers:

PLCC/PQFP type packages:

NET io_net_name LOC = P111 ;
NET HIERARCHY_BLOCK/io_net_name LOC = P44 ;


PGA/BGA type packages:

NET io_net_name LOC = A11 ;
NET HIERARCHY_BLOCK/io_net_name LOC = C12 ;

NOTE: The "P" is used only with PLCC/PQFP type packages.


Assigning an I/O pin to a selection of pin locations:

The following example assigns "io_net_name" to either P4, P5, or P6:

NET io_net_name LOC = P4, P5, P6 ;


To prohibit I/O pins C26 or CLBR5C3 from being used:

CONFIG PROHIBIT = C26 ;
CONFIG PROHIBIT = CLB_R5C3 ;


NOTE: The Mode pins (MD0, MD1, MD2) and the Boundary Scan pins [TCK, TDI, TDO, TMS] cannot be prohibited or assigned; an error might occur if these sites are prohibited from the UCF file. These sites are reserved sites and are used only if specified in the design.


Assigning Specific Logic Locations

Place 0.

A basic element (BEL) in a specific CLB. BEL = FF, LUT, RAM, etc.:

INST io_buf_name LOC = P110 ;
INST instance_path/BEL_name LOC = CLB_R17C36 ;

Assigning Area Constraints

XC3000 - Place CLB logic anywhere in the top-left corner of the device bounded by Row F and Column F:

INST logic_name LOC=AA:FF ;


XC4000 - Place logic in the top-left corner of the device in a 5x5 area bounded by Row 5 and Column 5:

INST logic_name LOC=CLB_R1C1:CLB_R5C5 ;


XC4000, XC5200 - Place a BUFT anywhere in the area bounded by Row 1, Column 1 and Row 2, Column 8:

INST logic_name LOC=TBUF_R1C1:TBUF_R2C8 ;


XC5200 - Place logic in any slice in the top-left corner of the device bounded by Row 4, Column 4:


INST logic_name LOC=CLB_R1C1.LC3:CLB_R4C4..LC0 ;

Multiple LOC constraint examples:

XC4000 - Place a decoder on the top or bottom edge:

INST logic_name LOC=T,B ;


XC4000, Virtex, Spartan - Place CLB logic in the top-left corner of the device in a 5x5 area, but not in the CLB, in Row 5, Column 5:

INST logic_name LOC=CLB_R1C1:CLB_R5C5 ;
INST logic_name PROHIBIT=CLB_R5C5 ;


XC4000, Virtex, Spartan - Place logic in any CLB in Column 8:

INST logic_name LOC=CLB_R*C8;


Specifying Miscellaneous Constraints for Logic or I/O

Fast or Slow Attributes

To assign an OBUF to be FAST or SLOW, use the following syntax:

INST obuf_name FAST ; #Alternate: NET pad_net FAST;
INST obuf_name SLOW ; #Alternate: NET pad_net SLOW;


MEDDELAY and NODELAY

To declare an IOB input FF delay (default = MAXDELAY), use the following syntax:

NOTE: You can attach MEDDELAY/NODELAY to a CLB FF that is pushed into an IOB by the "map -pr i" option.


INST input_ff_name MEDDELAY ;
INST input_latch_name NODELAY ;


In version 3.1i, the IOB input FF delay was changed; the options are IOBDELAY= NONE, IFD, IBUF, or BOTH, as follows:


INST input_ff_name IOBDELAY = Both;
INST input_latch_name IOBDELAY = IFD;


KEEP

To prevent a net from being absorbed into a logic block, use the following:

NET net_name KEEP ;


Net Flag (S attribute)

To prevent unconnected logic from being optimized out of a design (FPGAs only), use the following:

NET net_name S;


INIT

To initialize ROMs, RAMs, and registers, use the following:

INST ROM_name INIT = 5555;
INST FF_name INIT = S;
AR# 2449
Date Created 08/21/2007
Last Updated 01/28/2013
Status Active
Type General Article
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