The UCF files generated with the core do not constrain the design to the correct GTP tile for use with the ML505 evaluation card. What edits are needed to correctly constrain the design?
The ML505 Evaluation board has a x1 PCI Express connector that uses the MGT located at location GTPX0Y1. To target this card with the core generated by CORE Generator, you must have the correct location of the GTP and other associated logic in the UCF file.
The zip file below contains a UCF with the necessary constraints to target the ML505 evaluation board with the LogiCORE Endpoint for PCI Express v1.2:
Note that other files needed to implement the design on a PC are also included in this zip. See the README.txt and (Xilinx Answer 24492) for more information.